//$Id: multiplier_ast_wrap.v 329 2009-05-27 15:32:55Z LINKABIT\taylort $

//*******************************************************************************************

module multiplier_ast_wrap(
	input  wire		    clk,
	input  wire         reset_n,

    output wire         ast_sink_ready,
    input  wire [23:0]  ast_sink_data_a,
    input  wire [23:0]  ast_sink_data_b,
    input  wire         ast_sink_valid,
    input  wire [1:0]   ast_sink_error,
    input  wire			ast_sink_sop,
	input  wire			ast_sink_eop,
	input  wire	[5:0]	ast_sink_channel,

    input  wire         ast_source_ready,
    output wire [23:0]  ast_source_data,
    output reg          ast_source_valid,
    output reg  [1:0]   ast_source_error,
    output reg			ast_source_sop,
	output reg			ast_source_eop,
	output reg	[5:0]	ast_source_channel
);	

wire [47:0] output_result;
reg         internal_valid;
reg [1:0]   internal_error;
reg			internal_sop;
reg			internal_eop;
reg	[5:0]	internal_channel;
	
multiplier	multiplier_inst (
	.aclr   ( ~reset_n ),
	.clken  ( internal_valid ),
	.clock  ( clk ),
	.dataa  ( ast_sink_data_a ),
	.datab  ( ast_sink_data_b ),
	.result ( output_result )
	);

//only take the upper 24
assign ast_source_data = output_result[47:24];
	
//pass the ready signal through back to the original source	
assign ast_sink_ready = ast_source_ready;

//pipeline the valid and error signals
always @(posedge clk or negedge reset_n) 
begin
    if(~reset_n) begin
		internal_valid		<= 0;
		internal_error		<= 0;
		internal_sop		<= 0;
		internal_eop		<= 0;
		internal_channel	<= 0;
		ast_source_valid	<= 0;
		ast_source_error	<= 0;
		ast_source_sop		<= 0;
		ast_source_eop		<= 0;
		ast_source_channel	<= 0;		
    end
    else begin
		internal_valid		<= ast_sink_valid;
		internal_error		<= ast_sink_error;
		internal_sop		<= ast_source_sop;
		internal_eop		<= ast_source_eop;
		internal_channel	<= ast_source_channel;
		ast_source_valid	<= internal_valid;
		ast_source_error	<= internal_error;
		ast_source_sop		<= internal_sop;
		ast_source_eop		<= internal_eop;
		ast_source_channel	<= internal_channel;	
    end
end
	
endmodule
